1 aug-13-2004 n-channel logic level enhancement mode field effect transistor P3055LSG to-263 lead free niko-sem absolute maximum ratings (t c = 25 c unless otherwise noted) parameters/test conditions symbol limits units gate-source voltage v gs 20 v t c = 25 c 12 continuous drain current t c = 100 c i d 8 pulsed drain current 1 i dm 45 a avalanche energy l = 0.1mh e as 60 repetitive avalanche energy 2 l = 0.05mh e ar 3 mj t c = 25 c 43 power dissipation t c = 100 c p d 15 w operating junction & storage temperature range t j , t stg -55 to 150 lead temperature ( 1 / 16 ? from case for 10 sec.) t l 275 c thermal resistance ratings thermal resistance symbol typical maximum units junction-to-case r jc 2.6 junction-to-ambient r ja 60 case-to-heatsink r cs 0.6 c / w 1 pulse width limited by maximum junction temperature. 2 duty cycle 1 % electrical characteristics (t c = 25 c, unless otherwise noted) limits parameter symbol test conditions min typ max unit static drain-source breakdown voltage v (br)dss v gs = 0v, i d = 250 a 25 gate threshold voltage v gs(th) v ds = v gs , i d = 250 a 0.8 1.2 2.5 v gate-body leakage i gss v ds = 0v, v gs = 20v 250 na 1. gate 2. drain 3. source product summary v (br)dss r ds(on) i d 25 50m ? 12a g d s
2 aug-13-2004 n-channel logic level enhancement mode field effect transistor P3055LSG to-263 lead free niko-sem v ds = 20v, v gs = 0v 25 zero gate voltage drain current i dss v ds = 20v, v gs = 0v, t j = 125 c 250 a on-state drain current 1 i d(on) v ds = 10v, v gs = 10v 12 a v gs = 5v, i d = 12a 70 120 drain-source on-state resistance 1 r ds(on) v gs = 10v, i d = 12a 50 90 m ? forward transconductance 1 g fs v ds = 15v, i d = 12a 16 s dynamic input capacitance c iss 450 output capacitance c oss 200 reverse transfer capacitance c rss v gs = 0v, v ds = 15v, f = 1mhz 60 pf total gate charge 2 q g 15 gate-source charge 2 q gs 2.0 gate-drain charge 2 q gd v ds = 0.5v (br)dss , v gs = 10v, i d = 6a 7.0 nc turn-on delay time 2 t d(on) 6.0 rise time 2 t r v ds = 15v, r l = 1 ? 6.0 turn-off delay time 2 t d(off) i d ? 12a, v gs = 10v, r gs = 2.5 ? 20 fall time 2 t f 5.0 ns source-drain diode ratin gs and characteristics (t c = 25 c) continuous current i s 12 pulsed current 3 i sm 20 a forward voltage 1 v sd i f = i s , v gs = 0v 1.5 v reverse recovery time t rr 30 ns peak reverse recovery current i rm(rec) i f = i s , dl f /dt = 100a / s 15 a reverse recovery charge q rr 0.043 c 1 pulse test : pulse width 300 sec, duty cycle 2%. 2 independent of operating temperature. 3 pulse width limited by maximum junction temperature. remark: the product marked with ?P3055LSG?, date code or lot # orders for parts with lead-free plating can be placed using the pxxxxxxg parts name.
3 aug-13-2004 n-channel logic level enhancement mode field effect transistor P3055LSG to-263 lead free niko-sem
4 aug-13-2004 n-channel logic level enhancement mode field effect transistor P3055LSG to-263 lead free niko-sem to-263 (d 2 pak) mechanical data mm mm dimension min. typ. max. dimension min. typ. max. a 14.5 15 15.8 h 1.0 1.5 1.8 b 4.2 4.7 i 9.8 10.3 c 1.20 1.35 j 6.5 d 2.8 k 1.5 e 0.3 0.4 0.5 l 0.7 1.4 f -0.102 0.203 m 4.83 5.08 5.33 g 8.5 9 9.5 n
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